1. Field of the Invention
The invention relates in general to a memory. More particularly, this invention relates a semiconductor memory device with a fast write recovery circuit which greatly reduces the write recovery time.
2. Description of the Related Art
In a conventional semiconductor memory device such as a dynamic random access memory (DRAM), a waiting period of time is required for writing a last bit of data into the memory device through only a sense amplifier at one end before activating a precharge command and after a write cycle. This waiting period is very often prolonged. Thus, when the operation speed of the DRAM is enhanced, the last bit data is very often written into the memory device fragmentarily.
For example, as shown in FIG. 1, a circuit diagram of a conventional semiconductor memory device is illustrated. The semiconductor memory device includes a memory array 100 and a sense amplifier 110. In the FIG. WL1 to WLn indicate word lines, while BL and BLB are a pair of complementary bit lines. In addition, DL and DLB are a pair of complementary data lines. COL is a column select signal, NSA and PSA are corresponding sense amplified enabling signals. For example, while NSA is a low level ground signal, PSA is then a high level voltage signal.
In a precharge cycle, the bit lines BL and BLB are pulled to a voltage level VBLR (=1/2 VDDA). At the beginning of a write cycle, an arbitrary one of the word lines WL1 to WLn is selected by a row select signal. Meanwhile, the charges saved in the memory cell and the capacitors of bit line BL or BLB are shared to result in a voltage difference between the bit lines BL and BLB. Being amplified by the sense amplifier, the bit lines BL and BLB are pulled up to a high voltage simultaneously.
A column select signal COL and a write in pulse signal are then triggered, one of the datalines DL and DLB is pulled down to a low voltage and the corresponding bit line BL or BLB is pulled down to the low voltage too. The potential difference between the bit lines BL and BLB is then amplified by the sense amplifier. Meanwhile, the column select signal COL and the write pulse signal are turned off, data are written into the memory cell merely by the sense amplifier.
After writing a last bit of data, the memory cell pulls down the bit line WLn to a low voltage according to the precharge command and thus complete a write cycle. Thus, the bit lines BL and BLB are recovered to a precharge state (=1/2 VDDA). The time between the last bit of data and the precharge command is called a write recovery time. The write recover time enables the data to be written into the memory cell completely.
As the write cycles is getting shorter, the bandwidth of the write in pulse signal becomes narrower and the write recovery time is shortened, the data written into a memory cell is incompletely while a relative bit line is to cease a write operation to enter a precharge state before being fully pulled down to the low potential level or up to the high potential level. The possibility of device failure for memory device is thus greatly increased to obstruct the development of high writing operation speed. In other words, as the operation speed of a SRAM is quickened, the last bit of data written in the semiconductor memory device is fragmentary.